• News


    2022


    September 2022       NEW Journal Paper
    Our paper, "HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language", has been accepted to be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

    September 2022       New Conference Paper
    Our paper, "SecHLS: Enabling Security Awareness in High-Level Synthesis", has been accepted to be presented in 28th Asia and South Pacific Design Automation Conference (ASP-DAC'23).

    August 2022       NEW Position
    I will start a new position as research assistant professor at ECE Department in University of Florida, FL (Fall'22).

    July 2022       Organizing Service
    I will serve as the publicity chair of 2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST'23). Since 2008, IEEE HOST'23 is the premier symposium that facilitates the rapid growth of hardware-based security research and development.

    June 2022       Invited Talk (Webinar)
    I will give a talk at CAD4Security (CAD4Sec) workshop, co-located with 59th Design Automation Conference (DAC) on the HLS security, entitled as "Security of Hardware Generators: Secure from Construction".

    June 2022       BEST WiP Award
    Our paper, "Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers", was selected for the best work-in-progress (WiP) award at IEEE International Symposium on Hardware Oriented Security and Trust (HOST'22).

    May 2022       Organizing Service
    I will serve as the session chair (SESSION 5: Lock the Hardware Down!) in IEEE International Symposium on Hardware Oriented Security and Trust (HOST'22). Hope to see you in the HOST'22.

    April 2022       Organizing Service
    I will serve as the publicity chair of 1st workshop on Cad4Security (CAD4Sec). The workshop includes experts from industry, academia, and government to shed light on the need for and the recent progress on the development of automatic security CAD solutions in all levels of design abstractions. The workshop will also include demos on the recent CAD for security prepared, developed, built by academia and industry teams.

    March 2022       NEW Journal Paper
    As a part of Future Microelectronics Security Research Series, we published a comprehensive survey paper on logic locking, entitled as "Advances in Logic Locking: Past, Present, and Prospects".

    February 2022       New Conference Paper
    Our paper, "Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers", has been accepted to be presented (as a WiP) in IEEE International Symposium on Hardware Oriented Security and Trust (HOST'22).

    February 2022       New Book
    Our proposal on a new hands-on book on logic locking has been accepted by SpringLink Publication, entitled as "Understanding Logic Locking".
    The book will be available by mid of 2023.

    February 2022       New Conference Paper
    Our paper, "O'Clock: Lock the Clock via Clock-gating for SoC IP Protection", has been accepted to be presented in Design Automation Conference (DAC'22).

    January 2022       Invited Talk (Webinar)
    I will give a webinar at national Microelectronics security training (MEST) center on the state-of-the-art on hardware obfuscation and logic locking, entitled as "IP Protection through Logic Locking: What to Expect From the State-of-the-arts".

    January 2022       New Book Chapter
    Our contribution as an entry (chapter) of Encyclopedia of Cryptography, Security and Privacy, entitled as "Sequential and Combinational Satisfiability Attacks", has been published and is available on SpringLink publication platform.

    2021


    June 2021       PhD Final Defense
    I succesfully defended my PhD dissertation titled, "The Evolution of Logic Locking: Towards Next Generation Logic Locking Countermeasures". Ph.Done!!!

    May 2021       NEW Conference Paper
    Our paper, "RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits", has been accepted to be presented in Great Lakes Symposium on VLSI (GLSVLSI'21).

    April 2021       NEW Journal Paper
    Our paper, "From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains", has been accepted to be published in IEEE Access.

    March 2021       NEW Position
    I will join Florida Institute for Cybersecurity Research (FICS) at ECE Department in University of Florida, FL, as a post-doctoral research associate (Fall'21).

    February 2021       NEW Journal Paper
    Our paper, "Deep Graph Learning for Circuit Deobfuscation", has been accepted to be published in Frontiers in big Data (Frontier'21).

    February 2021       NEW Conference Paper
    Our paper, "Chaolock: Yet another sat-hard logic locking using chaos computing", has been accepted as a regular paper with oral presentation in 22nd International Symposium on Quality Electronic Design (ISQED'21).

    January 2021       Invited Talk (Webinar)
    I will give a webinar at cadforassurance.org on hardware security focused on, "Satisfiability Modulo Theory (SMT) Attack".

    January 2021       NEW Journal Paper
    Our paper, "Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits", has been accepted to be published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI).




    November 2020       BEST Paper Award
    Our paper, "ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things", selected for best paper award in 14th IEEE Circuits and System Conference (DCAS'20).

    September 2020       BEST Paper Nominee
    Our paper, "InterLock: An Intercorrelated Logic and Routing Locking", has been nominated for the best paper award at International Conference On Computer Aided Design (ICCAD'20).

    July 2020       NEW Conference Paper
    Our paper, "NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures", has been accepted as a regular paper with oral presentation in International Conference On Computer Aided Design (ICCAD'20).

    July 2020       NEW Conference Paper
    Our paper, "InterLock: An Intercorrelated Logic and Routing Locking", has been accepted as a regular paper with oral presentation in International Conference On Computer Aided Design (ICCAD'20).

    June 2020       BEST Paper Nominee
    Our paper, "SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption", has been nominated for the best paper award at IEEE Computer Society Annual Symposium on VLSI (ISVLSI'20).

    March 2020       Industrial Experience
    I will join Microchip Corporation (Virtual/Remote due to COVID-19) as research intern for Summer 2020.

    February 2020       NEW Conference Paper
    Our paper, "SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption", has been accepted as a regular paper with oral presentation in IEEE Computer Society Annual Symposium on VLSI (ISVLSI'20).

    February 2020       NEW Conference Paper
    Our paper, "On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic", has been selected as an invited talk to be presented in Great Lakes Symposium on VLSI (GLSVLSI'20).

    December 2019       NEW Conference Paper
    Our paper, "DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain", has been accepted as a regular paper with oral presentation in IEEE VLSI Test Symposium 2020 (VTS'20).

    December 2019       NEW Journal Paper
    Our paper, "SAT-hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain", has been accepted to be published at IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI).

    July 2019       BEST Paper Nominee
    Our paper, "Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality", has been nominated for the best paper award at International Conference On Computer Aided Design (ICCAD'19).

    June 2019       NEW Conference Paper
    Our paper, "Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality", has been accepted as a regular paper with oral presentation in International Conference On Computer Aided Design (ICCAD'19).

    May 2019       NEW Conference Paper
    Our paper, "COMA: Communication and Obfuscation Management Architecture", has been accepted as a regular paper with oral presentation in International Symposium on Research in Attacks, Intrusions and Defenses (RAID'19).

    May 2019       NEW Conference Paper
    Our paper, "Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers", has been accepted as a regular paper with oral presentation in ACM/IEEE Int'l Symposium on Low Power Electronics and Design (ISLPED'19).

    March 2019       Industrial Experience
    I will join Microchip Corporation at San Jose, CA, as research intern for Summer 2019.

    February 2019       NEW Conference Paper
    Our paper, "Threats on Logic Locking: A Decade Later", has been accepted in Great Lakes Symposium on VLSI (GLSVLSI'19), special issue on Hardware Security.

    February 2019       NEW Conference Paper
    Our paper, "Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks", has been accepted as a regular paper with oral presentation in Design Automation Conference (DAC'19).

    September 2018       NEW Journal Paper
    Our paper, "SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond The SAT Attacks", has been accepted as a regular paper with oral presentation in IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES 2019, Issue 1).

    May 2018       NEW Conference Paper
    Our paper, "SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers", has been accepted as a regular paper with oral presentation in ACM/IEEE Int'l Symposium on Low Power Electronics and Design (ISLPED'18).

    April 2018       NEW Conference Paper
    Our paper, "LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection", has been accepted as a regular paper with oral presentation in IEEE Computer Society Annual Symposium on VLSI (ISVLSI'18).

    February 2018       NEW Conference Paper
    Our paper, "SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware", has been accepted as a regular paper with oral presentation in Great Lakes Symposium on VLSI (GLSVLSI'18).

    February 2018       NEW Conference Paper
    Our paper, "MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture", has been accepted as a short paper with poster in Great Lakes Symposium on VLSI (GLSVLSI'18).

    August 2017       NEW Conference Paper
    Our paper, "SMART: A scalable mapping and routing technique for power-gating in NoC routers", has been accepted as a regular paper with oral presentation in IEEE/ACM International Symposium on Networks-on-Chip (NOCS'17).

    July 2017       NEW Journal Paper
    Our paper, "DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture", has been accepted in IEEE Transactions on Computers (TC).

    August 2016       NEW Journal Paper
    Our paper, "A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard", has been accepted in Journal of Circuits, Systems and Computers (JCSC).

    June 2016       NEW Conference Paper
    Our paper, "AdapNoC: A Fast and Flexible FPGA-based NoC Simulator", has been accepted as a regular paper with oral presentation in International Conference on Field-Programmable Logic and Applications (FPL'16).

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